Why we are building OhmSens.

Analog design has resisted abstraction longer than almost any other engineering discipline. You cannot hand-wave a low-noise front end. You cannot hallucinate phase margin. A circuit either works in the physics, or it does not, and a hundred years of accumulated craft sits between an idea and a sized, simulatable, manufacturable implementation.

Most of that craft is mechanical. Pick a topology that fits the spec. Snap component values to standard series. Write a netlist. Run a simulation. Read the curve. Decide if the curve matches the intent. If not, change one thing and try again. The engineer's judgement lives in steps one and six. Steps two through five are bookkeeping that a careful agent should be able to handle.

Two things changed in the last eighteen months. Frontier language models got reliable enough to draft real SPICE netlists with the right syntax, the right component values, and a defensible sense of which topology fits which spec. And open-source SPICE simulators, the same numerical engines that have powered serious analog work for forty years, still run in milliseconds on a laptop and give you ground truth at zero marginal cost.

Put those two together and you can build a different kind of tool. Not a drawing surface with a chat sidebar. Not a generative toy that produces plausible-looking schematics no one runs. A simulator that listens to natural-language intent, generates a real netlist, runs it, reads the result, and only shows you what the physics agreed with.

The simulator is the source of truth. The agent never overrides it. If the model disagrees with the math, the model is wrong, and the error feeds back into the loop until the netlist parses, the operating point converges, and the response curve is something we can plot. The retry budget is bounded so a stuck circuit fails loud instead of running forever.

That rule is the line between an engineering tool and a generative toy. A circuit that does not simulate is not a circuit, no matter how confidently a model describes it. We would rather show you the failure than smooth it over.

Type a circuit in plain English. The agent picks a topology, sizes the parts to standard E-series values, runs the simulation, draws the schematic, plots the response, and writes a short textbook-style design note explaining the why. You walk away with a netlist any SPICE-compatible tool can re-run, a schematic that drops into a lab report, and a one-link share for the TA or the colleague who is going to ask.

The first version covers the analog building blocks every working engineer touches every week: passives, RC and RLC filters, voltage dividers, op-amp gain stages, small-signal transistor amps. Twenty vetted reference circuits ship in the library, each one simulated and fact-checked before it goes in front of anyone. Opening one costs nothing because the artifact is already on disk.

Bring your own model key and the cost of inference goes straight to the provider. We do not sit in the middle of the inference bill. We sit in the middle of the loop that makes inference produce something defensible.

We are not pretending v1 covers full-stage RF, switched-mode power, mixed-signal blocks with serious digital state, or photonic design. We do not host production-grade DRC or LVS. We are not the right place to lay out a 200-pin board. If you are doing those things, keep your tooling and treat us as a faster way to sketch the analog islands inside it.

What we are building is the path from intent to a validated, exportable artifact short enough that an engineer can run it five times before lunch. The shortening changes how often you are willing to try things, and that changes how often you learn from the failed try.

The thing that resists abstraction is the thing whose abstraction is most valuable. Analog has resisted because the physics has no patience for plausible-sounding output. That is exactly why a careful agentic loop, one that defers to the simulator on every disagreement, is a different category of tool from anything previously possible here. The team that gets the loop right will sit under more analog engineering work than is obvious from the wedge it starts with.

We are not promising a magic chip-design assistant in a quarter. We are promising that every turn produces something the physics agreed with, and that the path from “I have an idea” to “I have an artifact a colleague can rerun” is the shortest one we know how to build.

One free run, no signup. Open the demo on the landing page, type the circuit you were about to draw by hand, and watch the loop close. If the simulator disagrees with the model, read the simulator output first. The simulator is right.